ARITHMETIC CIRCUITS AND COMPARATORS
This experiment seeks to:
– Examine how addition and subtraction are performed by the use of logic gates.
– Examine how binary numbers are compared using logic gates.
– Understand the working principle of comparators.
It is possible to implement binary arithmetic in hardware through the direct application of basic logic gates. This is through the manipulation of binary numbers using simple gates such as the AND and OR gates, for example, the AND gate can be used to realize a multiplication operation in the simplest form. On the hand, OR gates can perform the addition operation. The circuit that is used to perform an arithmetic operation is called an arithmetic circuit and can be either a combinational or a sequential circuit. This experiment is designed to facilitate the understanding that it is possible to realize arithmetic and other mathematical operations using logic gates. This is by way of building combinational and sequential circuits that take binary input operate on them and give the result of the arithmetic functions. Crucial circuits that will be simulated include the adder circuit, both half and full, and the comparator circuit.
A combinational circuit is one where the output at a given time depends only on the present state of the gates used in the circuit. The past state of the gates does not, in any way, determine the output. A set of Boolean expressions define the logical function of a combinational circuit. Examples of a combinational circuits are decoders, multiplexers, and Arithmetic Logic Unit (ALU), which operates on data in a computer. A decoder is a multi-input multi-output device that converts the input into an output according to a particular formula. On the other hand, sequential circuit comprise of both logic gates and memory elements such as flip flops and therefore the state of the output is determined by the current state of the logic gates as well as previous state of the gates. An example of a sequential circuit is a register.
A digital comparator circuit is composed of AND, NOR and NOR gates. This is a circuit that compares the digital signals present at their input terminals. Once their comparison is made, an output is produced which is dependent on the state of the inputs. The state at the input terminal A can be greater than, smaller than, or equal to the input at terminal B. For proper comparison to be conducted there has to be at least two inputs. However there are some comparators that have more than two inputs and these are used in complex computations.
There are two major types of comparators identity comparator and a magnitude comparator. An identity comparator is a digital comparator and has only one output terminal. The output is obtained as either when A = B = 1 or A = B = 0. A magnitude comparator on the other hand has three output terminals. The terminals represent each equality A = B, A < B or A > B. A magnitude comparator compares the magnitude of the two inputs hence cannot be fed with more than three inputs.
Equipment and Components Used
In the Multisim, the components used are:
– NOT gates
– AND gates
– OR gates
– A half adder
– Full adder
– Exclusive NOR gates
– Exclusive OR gates
– Connection wires
Experimental Method and Procedure
– The circuit E10-1.MS7, which is a half adder, was loaded onto the working space. This circuit is capable of adding two bits together and in the process generate a sum denotes as S and a carry denoted as C.
– The components were added so as to verify the operation of the half adder and the truth table drawn.
– The circuit E10-2.MS7 was then loaded from the miscellaneous digital parts bin. This circuit performs the same function as the half adder.
– The circuit was the tested and its operation verified.
– The circuit E10-3.MS7 was later loaded onto the workspace. This circuit is a full adder and it adds three bits together. The three inputs that are added are the two inputs as well as the carry.
– The Logic Converter was later used to test the full adder and the truth table was later drawn.
– After the above procedure, the circuit E10-5.MS7 was loaded and examined. This circuit is a 2-bit parallel adder and it adds two or more bits from two input numbers at the same time.
– The Ci input was grounded to apply a logic zero level and hence guaranteeing that the initial sum bit S0 is correct. The components required to test the 2-bit adder were added.
– A 4-bit parallel adder was made by cascading two copies of the 2-bit adder. The Co output of the 2-bit stage was connected to the Ci input of the second 2-bit stage.
– The 4-bit adder was modified into a 4-bit subtractor. This subtraction was performed using a 2’s complement arithmetic. The 4-bit adder was modified by inserting inverters on all the B inputs and by tying the Ci input high. 0111 was placed on the A inputs and 0011on the B inputs. The sum (S) output was confirmed to be 0100.
– The circuit E10-6.MS7, which uses exclusive NOR, was then loaded and used to perform comparison.
– The Eq output was verified to go low when the 4-bit input numbers are equal.
– The circuit E10-7.MS7, which is a magnitude comparator, was loaded and examined. This circuit is able to determine if two numbers are smaller than, equal to, or larger than one another.
– A 4-input Karnaugh map was used to design the less-than comparator with ones placed into each position where AA is less than B. This made the AB output to go high whenever A1A0 was less than B1B0.
– The required components were then added to test the less-than comparator and the Karnaugh map filled.
– Two copies of the circuit E10-7.MS7 plus some additional logic were used to make a 4-bit less than comparator. This additional circuit was required because the upper two bits of each number may be equal.
Observations and Results
Circuit E10-1.MS7 (Half adder)
The strobe is used to show the presence of the signal. The strobe lights when the signal is available indicating a 1 which is a high. The truth table below was drawn from the circuit above and represents the truth table of a half adder. This is as shown below
The truth table obtained is as shown below
The half adder equations to obtain the sum and carry are;
S = A’B + AB’ (XOR operation)
C = AB (AND)
The circuit E10-3.MS7, which is shown below, is a full adder produced the following truth table.
The truth table produced is
Circuit E10-4.MS7, which is a simplified full adder circuit, upon examination produced the following results
The truth table obtained was as shown below
As seen from the two truth tables, the simplified and the full adder circuit and the full adder circuit produce the same truth table.
The circuit E10-5.MS7 represents a parallel adder. A parallel adder is a digital circuit that computes the addition of variable binary strings of equivalent or different size in parallel.
– Difference between a half adder and a full adder
A half adder is an arithmetic circuit that is used to add two bits. It has two input for the bits to be added and two outputs. The two outputs represent the sum and carry. For any two inputs into the half adder, the two outputs, a sum and a carry must be present. The Boolean expression for the sum and carry are
Sum (S) = AB’ + A’B
Carry (C) = A.B
The truth table
A half adder is used for the addition of Least Significant Bits (LSBs).
A full adder is used to add three bits and produces a sum and a carry. The full adder overcomes the limitation of the half adder circuit in the sense that it is used to add binary numbers with a large number of bits. The full adder is used to add the Most Significant Bits (MSBs)
2. A parallel adder is used to add two or more bits from two input numbers at the same time. It is therefore necessary to have a full adder if more than two bits are to be added. By using a half adder, only two bits can be added.
3. In a subtractor, the 2s complement of a number is used to achieve the subtraction. This is done by first getting the complement of the number then adding 1 to it. By tying the Ci as a high, this is added to 1 then complementing it in order to achieve the 2s complement and in the process accomplish the subtraction. The subtraction is achieved by adding the 2s complement of the subtrahend to the number.
In comparison the gates used are AND, NOT and NOR gates. In an XNOR gate the Boolean expression for the operation is F = A’B’ + AB. As seen from the equation, the output is the inversion of the two input A and B inverted ANDed together and A and B ANDed together as well. The two resultant output ORed together. The operation of the NOR gate are hence used in the comparison.
The experiment was completed successfully. The operations of the comparators was investigated keenly and the various truth table drawn. The logic gates used in comparison are the NOT, AND and NOT gates. These three are combined in a combinational circuit and perform the required function. Various adders can be combined to perform a specific intended task. The performance of these tasks was found to conform to the expected result.
These arithmetic circuits and comparators have a wide range of operations in the modern world. They find a wide use in computers and registers. This emphasizes the importance of performing this experiment to cement knowledge of their operation. Lastly, the experiment was successful in meeting its objectives.
Saha, A., & Manna, N. (2007). Digital principles and logic design. Hingham, Mass: Infinity Science Press.
Sarkar, Subir Kumar, De, Asis Kumar, & Sarkar, Souvik. (2012). Foundation of Digital Electronics and Logic Design. Pan Stanford Pub.